If VDP1 was pipelined to allow writes to the framebuffer while fetching the next textel, that would certainly boost texture fill rate to similar speed as plain line filling (and perhaps faster than gouraud shading -depending on what logic was dedicated to that).
So a lot faster than I was thinking. (and also a much better match for the PSX GPU, for that matter -and could probably have made for a quite nice 2D engine for the time even without VDP2 . . . and obviously similarly capable in 3D as it already is)
Hmm, I wonder if the 3DO supports that too . . . that would be a much better use of the separate source and destination buses (VRAM for the framebuffer and shared DRAM for textures), or for that matter if it has 32-bit source and destination buffers to take advantage of the full bus width (or at least a destination buffer). In the 3DO's case, the max fillrate (with FPM and 32-bit optimizations) would be 25 Mpix/s for 16-bit pixels. (not sure of the actual 3DO texture performance though)
It's also odd that VDP1 would have separate buses for both framebufer banks though, since it would only be accessing 1 per-frame (with VDP2 accessing the other) . . . unless VDP1 also contains the bus-steering logic to flip the banks between VDP1 and VDP2 (except that would require an additional set of address/data lines to connect to VDP2 . . . though since it should just be scanning a linear framebuffer, that could be limited to a serial pixel bus -somewhat like VRAM uses)
Hmm, interesting, especially the dual bank support (which would make that slightly closer to SGRAM in some respects -except the banks are fixed, so more like 2 separate 128k chips with interleaving . . . which would also explain the odd 2Mbit density). That should mean the 32x could get a significant performance boost from having the master and slave SH2s work mostly in separate 128k banks of SDRAM (reducing page breaks).I found this quite interesting ( Saturn schematic )
along with a datasheet for the ram - which is SDRAM for VDP1 frame buffers.
seems to show single cycle burst writes...
The speed ratings confirm my previous knowledge on the Saturn/32x SDRAM . . . much faster rated speed than the system was actually clocked at. (in that respect, a single bus using the same SDRAM chips clocked at double the VDP speed could have performed similarly to the separate buses -assuming source/destination were still interleaved as separate banks . . . or double the current bandwidth if used at full speed and with simultaneous accessed on separate buses)
The 32x example is limited since the framebuffers are quite slow in general, and the CPUs wouldn't be reading and writing pixels simultaneously even if the buffers were at SDRAM speed. (ie you wouldn't even be able to do block copy faster than 11.5 M words/s)