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Thread: Instruction Cycle Timing: 68070 vs 68000

  1. #1
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    Default Instruction Cycle Timing: 68070 vs 68000

    Hi!

    I found this stuff the other day and felt like sharing it here.

    The Signetics 68070 processor was used on the Philips CD-i and I think a lot of people get the wrong notion that's either an evolution of the Motorola 68060 or a carbon-copy of the Motorola 68000.
    It's actually inferior to a Motorola 68000 in terms of instruction timing.
    Wikipedia says: The SCC68070 lacks a dedicated address generation unit (AGU), so operations requiring address calculation run slower due to contention with the shared ALU. This means that most instructions take more cycles to execute, for some instructions significantly more, than a 68000. But I don't know if that statement is accurate or not, and I couldn't find detailed info on it anywhere else.


    Code:
    INSTRUCTION CYCLE TIMES OF THE 68070 VERSUS THE 68000
    =====================================================
    
    The following file lists, in detail, the number of clock cycles required for
    each instruction of the Signetics SCC68070 and the Motorola MC68000.  The
    68070 is merely an instruction/register set clone of the 68000.  Signetics
    created their own CPU architecture to implement it.  So the cycle times for
    most instruction are different.  So this file will allow you to compare the
    two.  All I can say is that it's a good thing the MM/1 and TC/70 are cranking
    away at 15MHz!  I place this file totally in the public domain... copy away!
    
    Matthew Thompson
    Waterloo, Ontario, Canada
    
    Note: Only Instruction Cycle times are included, while the number of Bus
          Cycles required are omitted, as bus cycles are identical for the
          two chips.  This file also assumes you are already vaguely familiar
          with 680x0 assembly.
    
    
    REGISTER SET
    ------------
    
    The 68000 family has 8 32-bit data registers D0-D7 and 8 32-bit address
    registers A0-A7, one of which (A7) doubles as the stack pointer.  There
    is also a 32-bit program counter and an 8/16-bit condition code register.
    
    
    CLOCK SPEEDS
    ------------
    
    Computer        Clock (MHz)  CPU    Clock Cycle (nS)  Bus Cycle (nS)
    --------------  -----------  -----  ----------------  --------------
    MM/1 and TC/70     15        68070         67               267
    Amiga             * 7.14     68000        140               560
    Atari ST          * 8        68000        125               500
    Macintosh         * 7.68     68000        130               520
    
    *: This is for the regular, non-020/030/040 models.
    
    So to calculate the time it takes the CPU to do an instruction, just multiply
    the number of clock cycles by the above Clock Cycle time.  For instance, an
    unsigned divide would take 140nS*140 = 19.6 microseconds on the Amiga, while
    it would take only 67nS*130 = 8.7 microseconds on the MM/1 or TC/070.
    
    
    EFFECTIVE ADDRESS COMPUTATION TIMES
    -----------------------------------
    
    These times are the overhead for each addressing mode, apart from the
    instruction times themselves.  They include fetching any extension words,
    fetching/storing the actual pieces of data that they reference (operands),
    and the computation itself.  Note: The following times assume byte or word
    operand/data transfers.  For all modes EXCEPT the register direct modes,
    there is an additional 4 cycles for each mode if the operand is a longword
    (obviously since you nead to read another word ergo another bus cycle).
    
    Addressing Mode                                   68070     68000
    ----------------------------------------------    -----     -----
    Dn            Data Register Direct*               0         0
    An            Address Reg Driect*                 0         0
    (An)          Addr Reg Indirect                   4         4
    (An)+         Addr Reg Ind w/ Postincrement       4         4
    -(An)         Addr Reg Ind w/ Predecrement        7         6
    d16(An)       Addr Reg Ind w/ Displacement        11        8
    d8(An,Xn)**   Addr Reg Ind w/ Index               14        12
    (xxx).W       Absolute Short                      8         8
    (xxx).L       Absolute Long                       12        12
    d8(PC)+       Program Cntr Rel w/ Displacement    11        8
    d16(PC,Xn)**+ Program Cntr Rel w/ Index           14        10
    #<data>+      Immediate                           4         4
    +: Cannot be used as a destination, as it would be a program reference.
    *: No extra cycles are required to use these modes with a longword operand.
    **: The size of the index register never affects execution time.
    
    
    MOVE INSTRUCTION
    ----------------
    
    The most commonly used 680x0 instruction is MOV, or move, to move hunks
    of data around.  To base cycle time for a move is:
    
                               68070          68000
                               -----          -----
                                 7              4
    
    Then, to figure out exactly how many cycles a move takes, just add the
    effective address computation times for both the source and the destination,
    using the chart above for the correct CPU.
    
    Examples:                      68070                  68000
                                   --------------------   --------------------
    MOVE.L Dn,An                   7 + 0 + 0       = 7    4 + 0 + 0       = 4
    MOVE.W (An)+,-(An)             7 + 4 + 7       = 18   4 + 4 + 6       = 14
    MOVE.L (d8,PC,Xn),(d8,An,Xn)   7+(14+4)+(14+4) = 43   4+(10+4)+(10+4) = 32
    
    
    OTHER INSTRUCTIONS
    ------------------
    
    Beyond the move instruction, all other instructions allow only one of either
    the operand or the destination it affects to be a complex addressing mode.
    The other value is either a register or a hunk of immediate data.  IN ALL
    CASES where an effective address has to be computed, simply add the number
    of cycles for the given addressing mode.
    
    Note:  Times are given as 68070/68000 clock cycles.  The b/w stands for byte
           or word operands, while l is for longwords.  A '-' indicates the
           function is not implemented for that addressing mode.  Byte operations
           are not possible on address registers.  These conventions will be
           followed for the remainder of the file.
    
    Standard Instructions:
    
                    op<ea>,An   op<ea>,Dn    Dn,mdest<ea>
                    ---------   ---------    ------------
    ADD,ADDA b/w      7/8****      7/4          11/8
             l        7/6**        7/6**        15/12
    AND      b/w       -           7/4          11/8
             l         -           7/6**        15/12
    CMP,CMPA b/w      7/6****      7/4            -
             l        7/6          7/6            -
    EOR      b/w       -           7/4***       11/8
             l         -           7/8***       15/12
    OR       b/w       -           7/4          11/8
             l         -           7/6**        15/12
    SUB      b/w      7/8****      7/4          11/8
             l        7/6**        7/6**        15/12
    DIVS               -         169/158*         -
    DIVU               -         130/140*         -
    MULS               -          76/70*          -
    MULU               -          76/70*          -
    *: Maximum basic value added to word effective address time.
    **: On the 68000, the base time of 6 becomes 8 if the effective address
        move is register direct or immediate (on top of the original address
        compuation time).
    ***: Only available addressing mode is data register direct.
    ****: Word only.
    DIVS,DIVU: The divide routines on both chips vary only 10% between best and
               worst case.
    MULS,MULU: The routines on both chips take 38+2n cycles, where n is:
               MULU: n = number of ones in <effective address>.
               MULS: n = concatenate the <ea> with a zero as the LSB, n is
                     the resultant number of 10 or 01 patterns in the 17-bit
                     source (ie worst case is when source is $5555).
    
    Immediate Instructions:
    
                     op#,Dn    op#,An    op#,mdest<ea>
                     ------    ------    -------------
    ADDI     b/w      14/8        -          18/12
             l        18/16       -          26/20
    ADDQ     b/w       7/4       7/4*        11/8
             l         7/8       7/8         15/12
    ANDI     b/w      14/8        -          18/12
             l        18/14       -          26/20
    CMPI     b/w      14/8        -          14/8
             l        18/14       -          18/12
    EORI     b/w      14/8        -          18/12
             l        18/16       -          26/20
    MOVEQ    l         7/4        -            -
    ORI      b/w      14/8        -          18/12
             l        18/16       -          26/20
    SUBI     b/w      14/8        -          18/12
             l        18/16       -          26/20
    SUBQ     b/w       7/4       7/8*        11/8
             l         7/8       7/8         15/12
    *: Word only.
    
    Single Operand, Shift and Rotate Instructions:
    
                      Register    Memory*
                      --------    ------
    {CLR,NEG,  b/w      7/4        11/8
    NEGX,NOT}  l        7/6        15/12
    NBCD       b       10/6        14/8
    Scc        b/w     13/4        17/8
               l       13/6        14/8
    TAS        b       10/4        15/14
    TST        b/w      7/4         7/4
               l        7/4         7/4
    {ASR,ASL,  b/w     13/6+       14/8
    LSL,LSR,   l       13/8+         -
    ROL,ROR,
    ROXL,ROXR}
    *: Remember to add the effective address computation time.
    +: Add 2n cycles for number n of places shifted on the 68000, add 3n for
       the 68070.
    
    Bit Manipulation Instructions:
    
                     Dynamic              Static
                     Register* Memory+    Register* Memory+
                     --------  ------     --------  ------
    BCHG,BSET   b        -      14/8          -      21/12
                l      10/8***    -         17/12      -
    BCLR        b        -      14/8          -      21/12
                l      10/10**    -         17/14      -
    BTST        b        -       7/4          -      14/8
                l       7/6       -         14/10      -
    *: Maximum values, could be less, data addressing mode only.
    +: Remember to add the effective address computation time.
    
    Conditional Instruction Times:
    
         Displacement    Branch Taken     Branch Not Taken
         ------------    ------------     ----------------
    Bcc       b              13/10             13/8
              w              14/10             14/12
    BRA       b              13/10               -
              w              14/10               -
    BSR       b              17/18               -
              w              22/18               -
    DBcc   cc TRUE             -               14/12
           cc FALSE          17/10             17/14
    CHK       -              64/40+            19/10+
    TRAPV     -              55/34             10/4
    +: Remember to add the effective address computation time.
    
    JMP, JSR, LEA, PEA and MOVEM instructions:
    
           (An)  (An)+ -(An) d16(An) d8(An,Xn)+ (x).W (x).L d16(PC) d8(PC,Xn)*
           ----- ----- ----- ------- ---------- ----- ----- ------- ---------
    JMP     7/8    -     -    14/10     17/14   14/10 18/12  14/10    17/14
    JSR    18/16   -     -    25/18     28/22   25/18 29/20  25/18    28/22
    LEA     7/4    -     -    14/8      17/12   14/8  18/12  14/8     17/12
    PEA    18/12   -     -    25/16     28/20   25/16 29/20  25/16    28/20
    MOVEM+
     M->R  26/12 26/12   -    30/16     33/18   30/16 34/20  30/16    33/18
     R->M  23/8    -   23/8   27/12     30/14   27/12 31/16    -        -
    ~?*: The size of the index register never affects execution time.
    +: These are the base MOVEM values.  You need to add cycles for each register
       moved.  These are: 68070 cycles/register  68000 cycles/register
                          ---------------------  ---------------------
                Word                7                      4
                Longword           11                      8
    
    Multiprecision Instructions:
    
                        opDn,Dn     opM,M
                        -------     -----
    ADDX,SUBX    b/w      7/4       28/18
                 l        7/8       40/30
    CMPM         b/w       -        18/12
                 l         -        26/20
    ABCD,SBCD    b/w     10/6       31/18
                 l       10/6       31/18
    
    Miscellaneous Instructions:
    
                          Register    Memory
                          --------    ------
    {ANDI/EORI/ORI          14/20        -
     to CCR/SR}
    MOVE from SR             7/6        7/8+
    MOVE to SR/CCR          10/12      10/12+
    {EXT*, NOP, MOVE         7/4         -
     from/to USP,SWAP}
    EXG                     13/6         -
    LINK                    25/16        -
    RESET                  154/132       -
    RTE                     **/20        -
    RTR                     22/20        -
    RTS                     15/16        -
    STOP                    13/4         -
    UNLK                    15/12        -
    +: Remember to add the effective address computation time.
    *: Both word and longword size.
    **: Since the 68070 emulates 68010 bus error recovery, it is a little more
        complex to figure out:        68070 RTE
                                      ---------
                        Short format      39
                        Long format
                           no rerun      140
                           w/ rerun      146
                           TAS rerun     151
    
    Move Peripheral Instruction
    
                  Register -> Memory    Memory -> Register
                  ------------------    ------------------
    MOVEP   w           25/16                  22/16
            l           39/24                  36/24
    
    
    EXCEPTION PROCESSING TIMES
    --------------------------
    
                          Cycles
                          -------
    Address Error         158/50
    Bus Error             158/50
    Divide by Zero         64/38+
    Illegal Instruction    55/34
    Interrupt              65/44*
    Privelege Violation    55/34
    Coming out of RESET    43/40
    Trace                  55/34
    TRAP Instruction       52/34
    *: The interrupt acknowledge cycle is assumed to take 4 clock cycles. +: Remember to add the effective address computation time.
    Source: https://groups.google.com/forum/mess...A/J5ZPnWwa-c8J
    Last edited by Barone; 09-04-2015 at 02:40 PM.

  2. #2
    Comrade as in friend. Master of Shinobi ComradeOj's Avatar
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    Interesting, thanks for sharing!

    Making the 'MOVE' instruction take almost twice as long must have really killed performance. As it says, the MOVE instruction is extremely common. In fact, everything is much slower with the exception of the unsigned divide instruction. If they had to spare one instruction from being slower though, it would have been the MOVE instruction.

    The 68010 style error recover is also interesting. I'm sure this would cause a lot of the same compatibility issues that 68k software has when running on a 68010. That probably doesn't really matter though, since the 070 was really only used in the CD-I.

    From wikipedia:

    Code:
    Additions to the Motorola 68000 core include:
    
        Operation from 4 - 17.5 MHz
        Inclusion of a minimal, segmented MMU supporting up to 16 MB of memory
        Built-in DMA controller
        IC bus controller
        UART
        16-bit counter/timer unit
        2 match/count/capture registers allowing the implementation of a pulse generator, event counter or reference timer
        Clock generator
    I wonder if this was enough to make it worth using a slower CPU. I guess the 15MHZ clock can at least partly make up for the instructions taking more cycles. AFAIK some those additions could be built into other parts of the CD-I hardware. Maybe they did it to cut costs?
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  3. #3
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    Quote Originally Posted by ComradeOj View Post
    I guess the 15MHZ clock can at least partly make up for the instructions taking more cycles. AFAIK some those additions could be built into other parts of the CD-I hardware. Maybe they did it to cut costs?
    IDK why the heck Philips chose to go with such a shitty CPU but it really stinks IMO.

    While the higher clock could probably make up for the instructions taking more cycles when compared to much older systems like the Amiga or the Mega Drive, I see a huge problem in terms of porting 68000-designed code to it since the difference in the instructions cycles timing isn't linear at all; some instructions have closer timing when compared to the 68000 and some others take like twice the time. And the 68010's exception handling style on top of that.

    I've never understood why so few Amiga and Mega Drive games got ported to it, and also why the heck games like Flashback had serious frame rate and scrolling issues on it but now it seems pretty clear: its 15 MHz 68070 would be roughly equivalent to a 9-10 MHz 68000 at its best but code designed for the 68000 would probably lost a lot of its original optimization status when ported over since the "balance" of the instructions cycles times is quite different.
    Last edited by Barone; 09-04-2015 at 10:34 PM.

  4. #4
    Raging in the Streets goldenband's Avatar
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    Wow, that CPU seems like an absolute stinker! I can only guess why they would've chosen it, but it certainly goes some way toward explaining why programmers found the CD-i so unpleasant to work with.

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    Most likely, Phillips was most concerned with cost reduction and figured the CD-i would never be used for serious applications. Remember, it originally began as just a multimedia player, something you'd use a virtual encyclopedia with. Only after the CD-i was released did Phillips decide to try selling games on it.

  6. #6
    Smith's Minister of War Hero of Algol Kamahl's Avatar
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    It's also worth pointing out that the CDi doesn't really have a proper graphics chip, it can't even scroll the screen. It's like an Atari ST with more colours.

    That CPU is pulling double duty, and most of that duty involves moving memory around.

    Yikes.
    This thread needs more... ENGINEERS

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    If anything, games like Wand of Gamelon/Faces of Evil are all the more impressive once you realize how crippled the hardware is.

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    So, in terms of processing power, the CDi would be about on par with the Atari ST?. I wouldnt have minded stuff like the ST Turrican 2 running the same, but with hundreds of colors on CDi.

    Makes The Aprentice for CDi seem even more impressive, that one runs great and looks amazing...something about vertical scrolling being easier to do in software than horizontal scrolling, right?

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    It would be my guess that the CDi and ST are around the same level (other than colour and sound), which is quite sad when you think about it.
    This thread needs more... ENGINEERS

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    Damn I'm late to the party !

    Philips used that chip because Signetics = Philips :P
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    RasterSoft Dev Death Adder's minion cdoty's Avatar
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    Quote Originally Posted by Barone View Post
    IDK why the heck Philips chose to go with such a shitty CPU but it really stinks IMO.
    They made a ton of poor choices on the CDi. The 2 plane 8 bit graphics system was nice, but the CPU wasn't powerful enough to handle it. There also isn't any dedicated hardware, such as a blitter. The Amiga had the advantage of a very powerful blitter, and rough sprite hardware. It also had the copper, which is similar to the HDMA in the SNES.
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    Yuck

    Quote Originally Posted by Kamahl View Post
    It would be my guess that the CDi and ST are around the same level (other than colour and sound), which is quite sad when you think about it.
    That's probably not a bad assessment, neither had the power to drive the hardware without major programming efforts. Later STs had a blitter, but game developers really couldn't count on that.

    The CDi did have a 2 256 color layers, but required special tricks to get games to run full speed. There was also a 16 color layer mode, but I can remember the details.

    Early 386 PCs were about the same. An FM Town console could run circles around a PC with the same specs.
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